-- $Id: $
-- File name:   USB_RCVR.vhd
-- Created:     10/12/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Design Entry
-- Description: USB Peripheral Receiver.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity USB_RCVR is
  port( CLK : in std_logic;
      RST_N : in std_logic;
     D_PLUS : in std_logic;
    D_MINUS : in std_logic;
   R_ENABLE : in std_logic;
     R_DATA : out std_logic_vector (7 downto 0);
       FULL : out std_logic;
      EMPTY : out std_logic;
    R_ERROR : out std_logic;
     RCVING : out std_logic);
end USB_RCVR;

architecture structural of USB_RCVR is

--========--
-- DECODE --
--========--
component DECODE is
    port( CLK : in std_logic;
        RST_N : in std_logic;
       D_PLUS : in std_logic;
 SHIFT_ENABLE : in std_logic;
          EOP : in std_logic;
       D_ORIG : out std_logic);
end component;


--=============--
-- EDGE_DETECT --
--=============--
component EDGE_DETECT is
    port( CLK : in std_logic;
        RST_N : in std_logic;
       D_PLUS : in std_logic;
       D_EDGE : out std_logic);
end component;


--===========--
-- SHIFT_REG --
--===========--
component SHIFT_REG is
  port(
          CLK : in std_logic;
        RST_N : in std_logic;
 SHIFT_ENABLE : in std_logic;
       D_ORIG : in std_logic;
       CHK_IN : in std_logic;
     RCV_DATA : out std_logic_vector (7 downto 0));
end component;


--=======--
-- TIMER --
--=======--
component TIMER is
  port(
          CLK : in std_logic;
        RST_N : in std_logic;
       D_EDGE : in std_logic;
       RCVING : in std_logic;
 SHIFT_ENABLE : out std_logic);
end component;


--==========--
-- RCV_FIFO --
--==========--
component RCV_FIFO is
  port(
          CLK : in std_logic;
        RST_N : in std_logic;
     R_ENABLE : in std_logic;
     W_ENABLE : in std_logic;
       W_DATA : in std_logic_vector (7 downto 0);
       R_DATA : out std_logic_vector (7 downto 0);
        EMPTY : out std_logic;
         FULL : out std_logic);
end component;


--============--
-- EOP_DETECT --
--============--
component EOP_DETECT is
  port(
       D_PLUS : in std_logic;
      D_MINUS : in std_logic;
          EOP : out std_logic);
end component;


--=====--
-- RCU --
--=====--
component RCU is
  Port ( CLK : in std_logic;
       RST_N : in std_logic;
      D_EDGE : in std_logic;
         EOP : in std_logic;
SHIFT_ENABLE : in std_logic;
    RCV_DATA : in std_logic_vector (7 downto 0);
     CHK_OUT : out std_logic;
      RCVING : out std_logic;
    W_ENABLE : out std_logic;
     R_ERROR : out std_logic
        );
end component;


--Declare signals before you begin.
signal D_PLUS_temp : std_logic;
signal D_MINUS_temp : std_logic;
signal D_PLUS_IN : std_logic;
signal D_MINUS_IN : std_logic;


signal sig_SHIFT_ENABLE : std_logic;
signal sig_EOP : std_logic;
signal sig_D_ORIG : std_logic;
signal sig_D_EDGE : std_logic;
signal sig_RCV_DATA : std_logic_vector (7 downto 0);

--Connecting the RCVING signal to the wire sig_RCVING to distribute it instead of using the the output pin.
signal sig_RCVING : std_logic;

signal sig_W_ENABLE : std_logic;

signal R_ERROR_temp : std_logic;
signal sig_CHK : std_logic;


--=======================================================================================================

--Begin Processes?
begin
--=================--
-- Sync for D_PLUS --
--=================--
D_PLUS_Reg: process (CLK, RST_N)
 begin
   if (RST_N='0') then
     D_PLUS_temp <= '1';
   elsif (CLK'event and CLK='1') then
     D_PLUS_temp <= D_PLUS;
   end if;
 end process D_PLUS_Reg;

D_PLUS_RegTwo: process (CLK, RST_N)
 begin
   if (RST_N='0') then
     D_PLUS_IN <= '1';
   elsif (CLK'event and CLK='1') then
     D_PLUS_IN <= D_PLUS_temp;
   end if;
 end process D_PLUS_RegTwo;

--==================--
-- Sync for D_MINUS --
--==================--

D_MINUS_Reg: process (CLK, RST_N)
 begin
   if (RST_N='0') then
     D_MINUS_temp <= '1';
   elsif (CLK'event and CLK='1') then
     D_MINUS_temp <= D_MINUS;
   end if;
 end process D_MINUS_Reg;

D_MINUS_RegTwo: process (CLK, RST_N)
 begin
   if (RST_N='0') then
     D_MINUS_IN <= '1';
   elsif (CLK'event and CLK='1') then
     D_MINUS_IN <= D_MINUS_temp;
   end if;
 end process D_MINUS_RegTwo;


--=====================--
-- Flip-Flop for ERROR --
--=====================--

ERROR_Reg: process (CLK, RST_N, R_ERROR_temp)
 begin
   if (RST_N='0') then
     R_ERROR <= '0';
   elsif (CLK'event and CLK='1') then
     R_ERROR <= R_ERROR_temp;
   end if;
 end process ERROR_Reg;



--======================--
-- Flip-Flop for RCVING --
--======================--

RCVING_Reg: process (CLK, RST_N, sig_RCVING)
 begin
   if (RST_N='0') then
     RCVING <= '0';
   elsif (CLK'event and CLK='1') then
     RCVING <= sig_RCVING;
   end if;
 end process RCVING_Reg;


--=======================================================================================================

------------
-- DECODE --
------------
DCODE: DECODE port map(
          CLK => CLK,
        RST_N => RST_N,
       D_PLUS => D_PLUS_IN,
 SHIFT_ENABLE => sig_SHIFT_ENABLE,
          EOP => sig_EOP,
       D_ORIG => sig_D_ORIG);

-----------------
-- EDGE_DETECT --
-----------------
EDGE_DET: EDGE_DETECT port map(
          CLK => CLK,
        RST_N => RST_N,
       D_PLUS => D_PLUS_IN,
       D_EDGE => sig_D_EDGE);

---------------
-- SHIFT_REG --
---------------
SHIFT_REGISTER: SHIFT_REG port map(
          CLK => CLK,
        RST_N => RST_N,
 SHIFT_ENABLE => sig_SHIFT_ENABLE,
       D_ORIG => sig_D_ORIG,
       CHK_IN => sig_CHK,
     RCV_DATA => sig_RCV_DATA);

-----------
-- TIMER --
-----------
TIME_REG: TIMER port map(
          CLK => CLK,
        RST_N => RST_N,
       D_EDGE => sig_D_EDGE,  --I am not using the D_EDGE signal!!!!!!!
       RCVING => sig_RCVING,
 SHIFT_ENABLE => sig_SHIFT_ENABLE);

--------------
-- RCV_FIFO --
--------------
FIFO_REG: RCV_FIFO port map(
          CLK => CLK,
        RST_N => RST_N,
     R_ENABLE => R_ENABLE, -- connect it directly to the output pin R_ENABLE
     W_ENABLE => sig_W_ENABLE,
       W_DATA => sig_RCV_DATA, -- W_DATA is the 8-bit input from the SHIFT_REG Which is the signal sig_RCV_DATA
       R_DATA => R_DATA,
        EMPTY => EMPTY,
         FULL => FULL);

----------------
-- EOP_DETECT --
----------------
EOP_REG: EOP_DETECT port map(
       D_PLUS => D_PLUS_IN,
      D_MINUS => D_MINUS_IN,
          EOP => sig_EOP);

---------
-- RCU --
---------
RCU_REG: RCU port map(
          CLK => CLK,
        RST_N => RST_N,
       D_EDGE => sig_D_EDGE,
          EOP => sig_EOP,
 SHIFT_ENABLE => sig_SHIFT_ENABLE,
     RCV_DATA => sig_RCV_DATA,
       RCVING => sig_RCVING,
     W_ENABLE => sig_W_ENABLE,
      CHK_OUT => sig_CHK,
      R_ERROR => R_ERROR_temp);
      --R_ERROR => R_ERROR);


--=======================================================================================================

--RCVING <= sig_RCVING;

end structural;





































